Power delivery in modern integrated circuit (IC) systems has become increasingly complex as supply voltages fall and power demands become more variant. A number of modern microprocessor systems, for example, require load voltage to be dynamically adjusted in response to processing demand, with voltage overshoot/undershoot to be maintained within closely specified ranges as load voltages change. IC-based power regulation and delivery systems have been developed to meet these requirements.
FIG. 1 illustrates a prior-art IC-based power delivery system 100 that includes a controller IC 101 and multiple power-stage ICs 1031-103N. The controller IC 101 outputs respective pulse-width-modulated (PWM) control signals 108 (Pctrl1-PctrlN), shown for example in FIG. 2, to the power-stage ICs 1031-103N which respond by delivering respective currents to a load 119, each at a time and for a duration determined by the duty cycle of the corresponding PWM control signal. As shown in FIG. 2, each PWM control signal includes a pulse 122 per switching interval (TSWITCH), with the individual pulses 1221-122N delivered to each power-stage IC 1031-103N being phase staggered so that the power-stage ICs 103 deliver load current at different times. By this arrangement, power delivery systems may be constructed using as many power-stage ICs as necessary to meet the peak power requirements of a given application. Also, the controller may modify the duty cycle of the PWM control signals to dynamically increase/decrease power delivered to the load and thus respond to fluctuating power demand.
As shown in the detail view of power-stage IC 1031, each IC 103 includes an N-MOS (N-channel metal oxide semiconductor) power transistor 105, N-MOS bypass transistor 107 and an N-MOS gate driver circuit 109. The gate driver circuit 109 outputs an active-high drive-enable signal 110 (NDRV) to switch the N-MOS power transistor 105 to a conducting state, and thereby switchably couple power source, V+ (e.g., a 12-volt source), to a power output node 114 (VOUT) of the power-stage IC. The power output node 114 is coupled via inductor 115 (LF) to a variable-resistance load 119 (modeled by resistor RL), which is coupled between inductor 115 and a grounded return node 116 (Ret) of the power-stage IC. Filter capacitor 117 (CF) is coupled in parallel with the load 119 and, together with inductor 115, forms a lowpass filter for maintaining a relatively steady-state supply voltage (VLOAD 120) across load 119. In an embodiment, CF comprises a plurality of capacitors coupled in parallel.
Referring to FIGS. 1 and 3, the gate driver circuit 109 maintains the active-high drive-enable signal 110 (NDRV) for the duration of the control pulse 1221 conveyed in the PWM control signal 108 (the pulses 1221-1224 for an exemplary set of four power stage ICs are shown collectively in FIG. 3, with the pulses for ICs 1222-122N shown in dashed outline) so that the amount of current delivered to the load 119 by each power-stage IC 103 is proportional to the duty cycle of the corresponding PWM control signal, Pctrl1′-PctrlN (i.e., wider control pulse width yields more current to the load 119 per switching interval). As shown, the output voltage 114 quickly rises to the V+ level when the drive-enable signal 110 is raised. At the falling edge of the control pulse 1221, the drive-enable signal 110 is deasserted (thus concluding drive-enable pulse 126), switching off the N-MOS power transistor 105 and thus concluding the power-delivery interval for power stage 1031. Consequently, the current through inductor 115 begins to fall, resulting in a slightly negative voltage spike 132 (<0 v) during the dead time interval 130 between deassertion of the drive-enable signal 110 and assertion of the bypass signal 112 (NBYP). When the bypass signal 112 is asserted, bypass transistor 107 begins conducting to provide a shunt path for the inductor current, thus restoring the output voltage 114 to a level at or near the ground potential. The bypass transistor 107 is switched off (i.e., by deassertion of bypass signal 112, thus concluding bypass pulse 128) prior to assertion of the drive-enable signal 110 in the subsequent switching interval. During the bypass interval within power stage 1031 (i.e., during assertion of bypass signal 112), the power-delivery and bypass operations are repeated within the subsequent power stage ICs 1032-103N in response to phase-staggered control pulses 122 (1221-1224 in the diagram of FIG. 3), yielding the pulse waveforms shown in dashed outline at the respective VOUT nodes 114 of the power stage ICs.
A fault within any one of the power stages 1031-103N may prevent it from delivering a proper load current during its respective timing interval, resulting in fluctuation errors in VLOAD 120. Accordingly, faults within the controller 101 may result in miscued phase-staggered control pulses 1221-122N, also contributing to fluctuation errors in VLOAD 120. It is therefore desired for a means to detect and adjust for faults in both the power stages 1031-103N and the controller IC 101 without sacrificing the performance of the device.